CURRENT OPENINGS
1) Lead Physical Design Engineer :
Designation: Lead PD Engineer
Experience: 7+ years
Location: Hyderabad/Bangalore
Qualification: B.E / B.Tech/M.Tech
Responsibilities Include, But Not Limited To
- Hands-on technical ownership of SoC for top-down/bottom-up physical design integration
- Drive Sub-block/partition decisions, floorplan for the best PPAS
- Generate sub-block/partition interface budgets, review
- Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
- Proficient in package co-design concepts
- Implement timing and functional ECOs
- P&R, Extraction, Physical verification, work towards STA closure
- Build automation flows wherever needed/adapt to existing flows for re-use
- Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO
- Needs to be automation savvy with high expertise in one of the programming languages used in the industry
- Clearly know requisites for executing his/her job and lead by example
- Bring tangible improvement in TAT with better quality
- Mentor junior engineers
Minimum Qualifications:
- A deep understanding of backend digital design flow, even to build a flow
- Proficient in timing constraints, physical constraints
- Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
- Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/ICC2/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
- Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python is strongly preferred
- Must possess excellent debug skills, analytical skills and the ability to work independently.
- Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone
2) Senior Physical Design Engineer:
Designation: Sr.Engineer
Experience: 4-7 years
Location: Hyderabad/Bangalore
Qualification: B.E / B.Tech/M.Tech
Desired Skills :
- Solid understanding and working knowledge of the SOC design with solid experience in taping out designs
- Experience with 16nm finfet or smaller process nodes is strongly preferred
- Hands-on experience with synthesis, floor-planning, block and full chip implementation with the latest industry P&R/STA flows and tools
- Solid hands on experience with clock tree synthesis (CTS), multi-voltage, multi-clock designs and low power design
- Strong working knowledge of Formal Equivalency Checks, LP checks, timing constraints generation and debug, UPF
- Experience in block level floor-planning, implementing power grid and area/congestion optimization
- Sign-off experience with reliability, signal integrity, noise, timing, power, physical and DFM closure is an added advantage
- Implement timing and functional ECOs
- P&R, Extraction, Physical verification, work towards STA closure
- Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/ICC2/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
- Clearly know requisites for executing his/her job and lead by example
- Strong scripting/programming skills in Tcl, Perl, Shell, and/or Python is strongly preferred
- Strong interpersonal skills both written and verbal